1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof and, more specifically, to a semiconductor device including a gate electrode provided with a stack structure having a polycrystalline silicon layer doped with impurities, a barrier layer and a metal layer.
2. Description of the Background Art
With recent reduction in the size of semiconductor devices, a resistance of a gate electrode must also be reduced. To reduce the resistance of the gate electrode, a stack structure including metal with high melting point and polycrystalline silicon has been proposed. In the structure, a barrier layer is essentially required for preventing diffusion of impurities such as silicon in the polycrystalline silicon layer, phosphorus, boron, arsenic or the like into the metal layer. Thus, the gate electrode has three layers, that is, the metal layer, barrier layer and polycrystalline silicon layer. With such structure, the resistance of the gate electrode can be reduced.
However, the semiconductor device provided with the gate electrode having the above described multilayer structure suffers from the following problems. The problems will be described with reference to FIGS. 25 to 28.
As shown for example in FIG. 25, a conventional gate electrode 7 includes a tungsten (W) layer as a metal layer 5, a tungsten nitride (WN) layer as a barrier layer 4, and a polycrystalline silicon layer 3. A silicon nitride layer 6, which serves as a hard mask, may be formed on gate electrode 7.
Gate electrode 7 is formed by selectively etching polycrystalline silicon layer 3, barrier layer 4 and metal layer 5 formed on a semiconductor substrate 1 with a gate insulating layer 2 interposed by reactive ion etching. At the time, a fluorine containing gas is used for etching metal layer 5.
However, the fluorine containing gas is high in reactivity with tungsten nitride used for barrier layer 4, so that polycrystalline silicon layer 3 is also etched at the time of etching metal layer 5. Thus, controllability in etching is low.
Further, as the fluorine containing gas also etches and removes SiO.sub.2, if gate insulating layer 2 includes SiO.sub.2, it also etches and removes gate insulating layer 2. As a result, as shown in FIG. 25, a recess 16 (a hole in the gate insulating layer) is disadvantageously formed which passes through gate insulating layer 2 to semiconductor substrate 1.
In addition, etching metal layer 5 using silicon nitride layer as a mask is accompanied by the following program. If Cl.sub.2 /O.sub.2 plasma is used for etching metal layer 5 using silicon nitride layer 6 as a mask, an etch selectively of silicon nitride layer 6 and metal layer (W) 5 becomes small (&lt;2). As a result, a thickness of silicon nitride layer 6 is reduced as shown in FIG. 26.
As silicon nitride layer 6 serves as an etching stopper when forming a contact structure, which is called a self aligning contact, such reduction in the thickness of semiconductor nitride layer 6 decreases reliability of the semiconductor device.
To avoid this problem, silicon nitride layer must preliminary be provided with a large thickness. In this case, however, in addition to a reduction in a throughput when forming silicon nitride layer 6, a profile of impurities in underlying semiconductor substrate 1 disadvantageously changes by a thermal treatment when forming silicon nitride layer 6.
The conventional gate electrode structure further suffers from a problem that it is difficult to determine an end of the etching of a barrier layer 4 and metal layer 5. Generally, the etching end of W or WN is determined by detecting a change in luminescent intensity of fluorine in plasma or fluoride of W. However, when polycrystalline silicon layer 3 is provided under barrier layer 4 as in the case of the above mentioned gate electrode 7, the fluorine containing gas etches polycrystalline silicon layer 3. As a result, the change in luminescent intensity of fluorine near the etching end of barrier layer 4 and metal layer 5 is reduced.
Consequently, it becomes difficult to detect the etching end of barrier layer 4 and metal layer 5. As shown in FIG. 27, isotropic etching of polycrystalline silicon layer 3 by the fluorine containing gas excessively proceeds, and a side surface of polycrystalline silicon layer 3 is disadvantageously etched (side etching of the polycrystalline silicon layer). Thus, in addition to the increase in resistance of gate electrode 7, reliability of the semiconductor device decreases.
The conventional semiconductor device also suffers from the following problem. As shown in FIG. 28, an interlayer insulating layer 12 is formed to cover gate electrode 7. As an aspect ratio of gate electrode 7 is high, it is difficult to bury interlayer insulating layer 12 between gate electrodes 7. As a result, a void 17 may be formed in interlayer insulating layer 12. Void 17 causes a short circuit between interconnections, thereby decreasing reliability of the semiconductor device.
As described above, the conventional semiconductor device suffers from various problems associated with the decrease in reliability.